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MT90401
SONET/SDH System Synchronizer Data Sheet
Features
* * * Meets requirements of GR-253-CORE for SONET Stratum 3 and SONET minimum clock Meets requirements of GR-1244-CORE Stratum 3 Meets requirements of G.813 Option 1 and Option 2 for SDH Equipment Clocks (SEC) with external jitter attenuator Provides OC-3/STM-1, DS3, E3, 19.44MHz, DS2, E1, T1, 8kHz and ST-BUS clock outputs Accepts reference inputs from two independent sources Selectable 1.544MHz, 2.048MHz, 19.44MHz or 8kHz input reference frequencies Holdover accuracy of 0.02 ppm Adjustable output clock phase supporting master-slave arrangements Hardware or microprocessor control (8 bit microprocessor interface) 3.3V supply JTAG boundary scan
DS5421 ISSUE 5 May 2002
Ordering Information MT90401AB 80 Pin LQFP
-40 to +85C
Description
The MT90401 is a digital phase locked loop (DPLL) that is designed to synchronize SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The MT90401 is used to ensure that the timing of outgoing signals remains within the limits specified by Telcordia, ANSI and the ITU during normal operation and in the presence of disturbances on the incoming synchronization signals. The MT90401 can operate in free-run, locked or holdover mode. The loop filter corner frequency can be selected to suit SONET applications or to suit SDH applications. The MT90401 uses an external 20MHz oscillator as its master clock and it does not require external loop filter components. In Hardware Mode, the MT90401 can be controlled and monitored via external pins. In Microport Mode, a microprocessor can be used for more comprehensive control and monitoring.
* * * * * * * *
Applications
* * * * SONET/SDH Add/Drop multiplexers SONET/SDH uplinks Integrated access devices ATM edge switches
TCLR
LOCK Virtual Reference
VDD
VSS
C20i TCK TDI TMS TRST TDO PRI SEC Prioor Secoor
Master Clock
IEEE 1149.1a
TIE Corrector Circuit Selected Reference TIE Corrector Enable Reference Select
DPLL Output Interface Circuit State Select Input Impairment Monitor
Reference Select MUX
Reference Monitor
State Select
C155P/N C19o C1.5o C2o C4o C6o C8o C16o C44/C34 F0o F8o F16o
Feedback Frequency Select MUX
RSEL
Control State Machine
RST MS1 MS2 HOLDOVER PCCi FLOCK D0/D7 A0/A6 CS,DS,R/W
FS1
FS2
Figure 1 - Functional Block Diagram
1
MT90401
IC DS FLOCK LOCK PCCi HOLDOVER VDD4 C34/C44 VSS7 C20i NC VDD3 TCLR RSEL C19o VSS5 IC C6o C1.5o PRIOOR
Data Sheet
SECOOR OE CS RST HW D0 D1 D2 D3 VSS8 IC IC VDD5 D4 D5 D6 D7 R/W A0 IC
60 62
58
56
54
52
50
48
46
44
42 40 38
64 36 66 34 68 70 72 28 74 26 76 24 78 22 80 2 4 6 8 10 12 14 16 18 20
MT90401AB
32 30
FS1 FS2 Tdi Trst Tclk Tms Tdo VREF VSS4 C155P C155N VDD VDD2 VSS3 IC VSS2 PRI SEC E3/DS3 E3DS3/OC3
IC A1 A2 A3 A4 VSS9 A5 A6 SONET/SDH VDD1 VSS1
F16o C16o C8o C4o C2o F0o
Figure 2 - Pin Connections 80 Pin LQFP for MT90401
Pin Description
Pin # 1 2-5 6 7, 8 9 Name IC A1 - A4 VSS9 A5, A6 SONET/ SDH Description Internal Connection. Leave unconnected. Address 1 to 4 (5V tolerant Inputs). Address inputs for the parallel processor interface. Digital ground. 0 Volts Address 5, to 6 (5V tolerant Input). Address inputs for the parallel processor interface. SONET/SDH (Input). In hardware mode set this pin high to have a loop filter corner frequency of 70 millihertz and limit the phase slope to 885 ns per second. Set this pin low to have a corner frequency of approximately 1.1 hertz and limit the phase slope to 53 ns per 1.326 ms. This pin performs no function if the device is not in hardware mode. Positive Power Supply. Digital supply. Digital ground. 0 Volts Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output). This is an 8kHz 61ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS operation at 8.192 Mb/s. Clock 16.384MHz (CMOS Output). This output is used for ST-BUS operation with a 16.384MHz clock. Clock 8.192MHz (CMOS Output). This output is used for ST-BUS operation at 8.192Mb/s. Clock 4.096MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s and 4.096Mb/s.
10 11 12
VDD1 VSS1 F16o
13 14 15
C16o C8o C4o
2
MS1
MS2 F8o
Data Sheet
Pin Description (continued)
Pin # 16 17 Name C2o F0o Description
MT90401
Clock 2.048MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s. Frame Pulse ST-BUS 2.048Mb/s (CMOS Output). This is an 8kHz 244ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS operation at 2.048Mb/s and 4.096Mb/s. Mode/Control Select 1 (Input). This input, together with MS2, determines the state (Normal, Holdover, or Freerun) of operation. See Table 3 on page 10. The logic level at this input is gated in by the rising edge of F8o. This pin performs no function if the device is not in hardware mode. Mode/Control Select 2 (Input). This input, together with MS1, determines the state (Normal, Holdover or Freerun) of operation. See Table 3 on page 10. The logic level at this input is gated in by the rising edge of F8o. This pin performs no function if the device is not in hardware mode. Frame Pulse Generic (CMOS Output). This is an 8kHz 122ns active high framing pulse, which marks the beginning of a TDM frame. This is typically used for TDM streams operating at 8.192 Mb/s.
18
MS1
19
MS2
20
F8o
21
E3DS3/OC3 E3DS3 or OC-3 Selection (Input). In Hardware Mode a low on this pin enables the differential 155.52MHz output clock on the C155N/C155P pins; this will also cause the C34/ C44 pin to output its nominal clock frequency divided by 4. In Hardware Mode, a high on this pin disables the differential 155.52MHz output clock on the C155N/C155P pins; this will also cause the C34/C44 pin to output its nominal clock frequency. This pin performs no function if the device is not in Hardware Mode. E3/DS3 E3 or DS3 Selection (Input). In Hardware Mode a low on this pin selects a clock rate of 44.736MHz for the C34/C44 pin, while a high selects a clock rate of 34.368MHz. This pin performs no function if the device is not in hardware mode. Secondary Reference (Input). This is one of two (PRI & SEC) input reference sources (falling edge) used for synchronization. One of four possible frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be used. In hardware mode the selection of the input reference is based upon the MS1, MS2 and RSEL control inputs. Primary Reference (Input). This is one of two (PRI & SEC) input reference sources (falling edge) used for synchronization. One of four possible frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be used. In hardware mode the selection of the input reference is based upon the MS1, MS2 and RSEL control inputs. Digital ground. 0 Volts Internal Connection. Leave unconnected Analog ground. 0 Volts Positive Analog Power Supply. Analog supply. Positive Power Supply. Digital supply. LVDS 155.52 MHz (Output)). Differential outputs generating a 155.52MHz clock Digital ground. 0 Volts LVDS Reference Voltage (Input). IEEE 1149.1a Test Data Output (Output). If not used, this pin should be left unconnected. IEEE 1149.1a Test Mode Selection (Input). If not used, this pin should be pulled high. IEEE 1149.1a Test Clock Signal (Input). If not used, this pin should be pulled high.
3
22
23
SEC
24
PRI
25 26 27 28 29 30 31 32 33 34 35 36
VSS2 IC VSS3 VDD2 VDD C155N, C155P VSS4 VREF Tdo Tms Tclk
MT90401
Pin Description (continued)
Pin # 37 38 39 Name Trst Tdi FS2 Description
Data Sheet
IEEE 1149.1a Reset Signal (Input). If not used, this pin should be held low. IEEE 1149.1a Test Data Input (Input). If not used, this pin should be pulled high. Frequency Select 2 (Input). This input, in conjunction with FS1, selects which of four possible frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be input to the PRI and SEC inputs. See Table 1 on page 6. Frequency Select 1 (Input). This input, in conjunction with FS2, selects which of four possible frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be input to the PRI and SEC inputs. See Table 1 on page 6. Primary Reference Out Of Range (CMOS Output). A logic high at this pin indicates that the primary reference is off the PLL center frequency by more than 12 ppm. The measurement is done on a 1 second basis using a signal derived from the 20MHz clock input on C20i. When the accuracy of the 20MHz clock is 4.6ppm, the effective out of range limits of the PRIOOR signal will be +16.6ppm to -7.4ppm or +7.4ppm to -16.6ppm. Clock 1.544MHz (CMOS Output). This output is used in T1 applications. Clock 6.312MHz (CMOS Output). This output is used for DS2 or J2 applications. Internal Connection. Tie low for normal operation. Digital ground. 0 Volts Clock 19.44MHz (CMOS Output). This output is used in OC-N and STM-N applications. Reference Source Select (Input). A logic low selects the PRI (primary) reference source as the input reference signal and a logic high selects the SEC (secondary) input. The logic level at this input is gated in by the rising edge of F8o. TIE Circuit Clear (Input). A logic low at this input clears the Time Interval Error (TIE) correction circuit resulting in a realignment of output phase with input phase. The TCLR pin should be held low for a minimum of 300ns. When this pin is held low, the time interval error correction circuit is disabled. Positive Power Supply. Digital supply. No Connection. 20 MHz Clock Input (5V tolerant Input). This pin is the input for the master 20MHz clock. Digital ground. 0Volts Controlled Clock 34.368MHz / Clock 44.736MHz (CMOS Output). This output clock is programmable to be either 34.368MHz (for E3 applications) or 44.736MHz (for DS3 applications). The output clock is controlled via control pins in Hardware Mode or control bits when the device is in Microport Mode. If the E3DS3/OC3 control pin or control bit is high, the C34/C44 pin will output its nominal frequency. If the E3DS3/OC3 control pin or bit is low, the C34/C44 pin will output its nominal frequency divided by 4. (C8.5o/C11o)
40
FS1
41
PRIOOR
42 43 44 45 46 47
C1.5o C6 IC VSS5 C19o RSEL
48
TCLR
49 50 51 52 53
VDD3 NC C20i VSS7 C34/C44
54 55 56
VDD4 PCCi
Positive Power Supply. Digital supply.
HOLDOVER Holdover (CMOS Output). This output goes high when the device is in holdover mode. Phase Continuity Control Input (3V Input). The signal at this pin affects the state changes between Primary Holdover Mode and Primary Normal Mode and Primary Holdover Mode and Secondary Normal Mode. The logic level at this input is gated by the rising edge of F8o. See "Figure 12 - Control State Diagram" on page 13 for details.
4
Data Sheet
Pin Description (continued)
Pin # 57 58 Name LOCK FLOCK Description
MT90401
Lock Indicator (CMOS Output). This output goes high when the PLL is in frequency lock to the input reference. Fast Lock Mode (Input). In hardware mode, hold this pin high to lock faster than normal to the input reference. This pin performs no function if the device is not in hardware mode. In Fast Lock Mode, the wander generation of the PLL is, of necessity, compromised. Data Strobe (5V tolerant Input). This input is the active low data strobe of the Motorola processor interface. Internal Connection. Tie low for normal operation. Secondary Reference Out Of Capture Range (CMOS Output). A logic high at this pin indicates that the secondary reference is off the PLL center frequency by more than 12 ppm. The measurement is done on a 1 second basis using a signal derived from the 20MHz clock input on the C20i pin. When the accuracy of the 20MHz clock is 4.6ppm the effective out of range limits of the SECOOR signal will be +16.6ppm to -7.4ppm or +7.4ppm to -16.6ppm. Output Enable (Input). Tie high for normal operation. Tie low to force output clocks pins F16, F8, C16, C8, C4, C2 to a high impedance state. Chip Select (5V tolerant Input). This active low input enables the non-multiplexed Motorola parallel microprocessor interface of the MT90401. When CS is set to high, the microprocessor interface is idle and all bus I/O pins will be in a high impedance state. RESET (5V tolerant Input). This active low input puts the MT90401 in a reset condition. RST should be set to high for normal operation. The MT90401 should be reset after powerup and after the selected reference frequency is changed. The RST pin must be held low for a minimum of 1sec. to reset the device properly. Hardware Mode (Input). If this pin is tied low, the device is in microport mode and is controlled via the microport. If it is tied high, the device is in hardware mode and is controlled via the control pins MS1, MS2, FS1, FS2, FLOCK and SONET/SDH. Data 0 to Data 3 (5V tolerant Three-state I/O). These signals combined with D4-D7 form the bidirectional data bus of the parallel processor interface (D0 is the least significant bit). Digital ground. 0 Volts. Internal Connection. Tie low for normal operation. Internal Connection. Tie low for normal operation. Positive Power Supply. Digital supply. Data 4 to Data 7 (5V tolerant Three-state I/O). These signals combined with D0-D3 form the bidirectional data bus of the parallel processor interface (D7 is the most significant bit). Read/Write Select (5V tolerant Input). This input controls the direction of the data bus D[0:7] during a microprocessor access. When R/W is high, the parallel processor is reading data from the MT90401. When low, the parallel processor is writing data to the MT90401. Address 0 (5V tolerant Input). Address input for the parallel processor interface. A0 is the least significant input. Internal Connection. Tie low for normal operation.
59 60 61
DS IC SECOOR
62 63
OE CS
64
RST
65
HW
66-69 70 71 72 73 74-77 78
D0 - D3 VSS8 IC IC VDD5 D4 - D7 R/W
79 80
A0 IC
5
MT90401
Functional Description
The MT90401 is a SONET/SDH System Synchronizer, providing timing (clock) and synchronization (frame) signals to interface circuits for Digital Telecommunications Transmission links. Figure 1 is a functional block diagram which is described in the following sections. Reference Select MUX Circuit The MT90401 accepts two simultaneous reference input signals and operates on their falling edges. Either the primary reference (PRI) signal or the secondary reference (SEC) signal can be selected as input to the TIE Corrector Circuit. The selection is based on the Control, Mode and Reference Selection of the device. See Table 1 and Table 4. Frequency Select MUX Circuit The MT90401 operates with one of four possible input reference frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz). The frequency select inputs, FS1 and FS2, which come from pins in hardware mode and control bits in microport mode determine which of the four frequencies may be used at the reference inputs (PRI and SEC). Both inputs must have the same frequency applied to them. A reset (RST) must be performed after every frequency select input change. See Table 1 - Input Frequency Selection. FS2 0 0 1 1 FS1 0 1 0 19.44MHz 8kHz 1.544MHz
Data Sheet
Input Frequency
1 2.048MHz Table 1. Frequency Selection
Time Interval Error (TIE) Corrector Circuit The TIE corrector circuit, when enabled, prevents a step change in phase on the input reference signals (PRI or SEC) from causing a step change in phase at the input of the DPLL block of Figure 1. During reference input rearrangement, such as during a switch from the primary reference (PRI) to the secondary reference (SEC), a step change in phase on the input signals will occur. A phase step at the input of the DPLL would lead to unacceptable phase changes in the output signal. As shown in Figure 3, the TIE Corrector Circuit receives one of the two reference (PRI or SEC) signals, passes the signal through a programmable delay line, and uses this delayed signal as an internal virtual reference, which is input to the DPLL. Therefore, the virtual reference is a delayed version of the selected reference. During a switch from one reference to the other, the State Machine first changes the mode of the device from Normal to Holdover. In Holdover Mode, the DPLL no longer uses the virtual reference signal, but generates an
TCLR Resets Delay Control Circuit Control Signal
Delay Value
PRI or SEC from Reference Select Mux
Programmable Delay Circuit
Virtual Reference to DPLL Compare Circuit
TIE Corrector Enable from State Machine
Feedback Signal from Frequency Select MUX
Figure 3 - TIE Corrector Circuit
6
Data Sheet
Virtual Reference from TIE Corrector Phase Detector Phase Slope Limiter Loop Filter Digitally Controlled Oscillator
MT90401
DPLL Reference to Output Interface Circuit
Feedback Signal from Frequency Select MUX
State Select from Input Impairment Monitor
Control Circuit
State Select from State Machine
Figure 4 - DPLL Block Diagram accurate clock signal using storage techniques. The Compare Circuit then measures the phase delay between the current phase (feedback signal) and the phase of the new reference signal. This delay value is passed to the Programmable Delay Circuit (See Figure 3). The new virtual reference signal is now at the same phase position as the previous reference signal would have been if the reference switch had not taken place. The State Machine then returns the device to Normal Mode. The DPLL now uses the new virtual reference signal, and since no phase step took place at the input of the DPLL, no phase step occurs at the output of the DPLL. In other words, reference switching will not create a phase change at the input of the DPLL, or at the output of the DPLL. Since internal delay circuitry maintains the alignment between the old virtual reference and the new virtual reference, a phase error may exist between the selected input reference signal and the output signal of the DPLL. This phase error is a function of the difference in phase between the two input reference signals during reference rearrangements. Each time a reference switch is made, the delay between input signal and output signal will change. The value of this delay is the accumulation of the error measured during each reference switch. The programmable delay circuit can be reset to zero by applying a logic low pulse to the TIE Circuit Clear (TCLR) pin. A minimum reset pulse width is 300ns. This results in a phase realignment between the input reference signal and the output signal as shown in Figure 16. The speed of the phase alignment correction is limited to 885 ns/s in SONET mode and 53ns per 1.326 ms in SDH mode, convergence is in the direction of least phase travel. The state diagram of Figure 7 indicates the state changes for which the TIE Corrector Circuit is activated. Digital Phase Lock Loop (DPLL) As shown in Figure 4, the DPLL of the MT90401 consists of a Phase Detector, Phase Slope Limiter, Loop Filter, Digitally Controlled Oscillator, and a Control Circuit. Phase Detector - the Phase Detector compares the virtual reference signal from the TIE Corrector circuit with the feedback signal from the Frequency Select MUX circuit, and provides an error signal corresponding to the phase difference between the two. This error signal is passed to the Phase Slope Limiter circuit. The Frequency Select MUX allows the proper feedback signal to be externally selected (e.g., 8kHz, 1.544MHz, 2.048MHz or 19.44MHz). Phase Slope Limiter - the Phase Slope Limiter receives the error signal from the Phase Detector and ensures that the DPLL responds to all input transient conditions with a limited output phase slope. In SONET Mode the maximum output phase slope is limited to 885ns/s as per Telcordia GR-253CORE. In SDH Mode the maximum output phase slope is 53ns per 1.326ms. Loop Filter - the Loop Filter is a low pass filter, that defines the network jitter and wander transfer requirements for all input reference frequencies (8kHz, 1.544MHz, 2.048MHz, or 19.44MHz). In SONET mode the loop filter has a cut-off frequency of 70mHz to comply with Telcordia GR-253-CORE and GR-1244-CORE. In SDH mode the loop filter has a cut-off frequency of 1.1Hz to comply with ITUT G.813 Option 1 and GR-1244-CORE.
7
MT90401
Control Circuit - the Control Circuit uses status and control information from the State Machine and the Input Impairment Circuit to set the mode of the DPLL. The three possible modes are Normal, Holdover and Freerun. Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop Filter, and based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is dependent on the state of the MT90401. In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input reference signal. In Holdover Mode, the DCO is free running at a frequency equal to the last locked frequency the DCO was generating while in Normal Mode. In order to improve accuracy of the Holdover Mode the actual frequency sample is taken 30-60ms before switching into holdover. In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the C20i 20MHz source. Telcordia GR-253-CORE requires that, during recovery from holdover, SONET clocks not change their output frequency at a rate faster than 2.9ppm per second. In SONET Mode the MT90401 limits the rate of change of its output frequency (frequency slope) to less than 1.9ppm per second; this limit remains in place when the PLL is in Fast Lock Mode. Lock Indicator - If the PLL is in frequency lock (frequency lock means the center frequency of the PLL is identical to the line frequency), and the input phase offset is small enough such that no phase slope limiting is exhibited, then the lock signal will be set high. Output Interface Circuit The output of the DCO (DPLL) is used by the Output Interface Circuit to provide the output signals shown in Figure 5. The Output Interface Circuit uses five Tapped Delay Lines in MT90401 followed by a T1 Divider Circuit, an E1 Divider Circuit, a DS2 Divider Circuit, and a x4/x8 PLL, to generate the required output signals. Five tapped delay lines are used to generate 8.592MHz, 11.184MHz, 16.384MHz, 12.352MHz, 12.624MHz and 19.44 MHz signals.
Data Sheet
The E1 Divider Circuit uses the 16.384MHz signal to generate four clock outputs and three frame pulse outputs. The C8o, C4o and C2o clocks are generated by simply dividing the C16o clock by two, four and eight respectively. These outputs have a nominal 50% duty cycle. The frame pulse outputs (F0o, F8o, and F16o) are generated directly from the C16 clock. The T1 Divider Circuit uses the 12.352MHz signal to generate C1.5o. This output has a nominal 50% duty cycle. The DS2 Divider Circuit uses the 12.624 MHz signal to generate the clock output C6o. This output has a nominal 50% duty cycle. The 19.44MHz signal is output on the C19o pin and it is multiplied by an internal PLL to generate the 155.52MHz clock output on the C155P/N pins. The C155P/N clock has a nominal 50% duty cycle. The 8.592MHz and 11.184 MHz signals are multiplied by an internal PLL to generate the 34.368MHz or 44.736MHz clock output on the C34/ C44 pin. If the internal PLL is dedicated to the C155P/N clock then the C34/C44 pin will output the 8.592MHz or 11.184 MHz clocks. The 34.368Mhz and 44.736MHz clocks have a nominal 50% duty cycle. The duty cycles of the 8.592MHz and 11.184MHz signals are dependent on the duty cycle of the 20MHz clock input to the C20i pin.
8
Data Sheet
MT90401
12MHz C1.5o
T1 Divider
Tapped Delay Line
Holdover Mode. The amount of phase drift while in holdover is negligible because the Holdover Mode is very accurate (i.e., 0.02ppm). Consequently, the phase delay between the input and output after switching back to Normal Mode is preserved. State Machine Control
From DPLL
Tapped Delay Line
16MHz
E1 Divider
C2o C4o C8o C16o F0o F8o F16o
Tapped Delay Line
12MHz DS2 Divider
C6o
An internal state machine can be enabled to control the TIE Corrector Circuit as shown in Figure 1. In hardware mode, control is based on the logic levels at the control inputs RSEL, MS1, MS2 and PCCi (See Figure 6). In Microport mode, control is based on the state of control bits RSEL, MS1 and MS2 and the PCCi pin. When switching from Primary Holdover to Primary Normal, the TIE Corrector Circuit is enabled when PCCi = 1, and disabled when PCCi = 0. All state machine changes occur synchronously on the rising edge of F8o. See the Control and Mode of Operation section for full details.
To Reference Select MUX To TIE Corrector Enable Control State Machine To DPLL State Select
Tapped Delay Line
19MHz
C19o
Tapped Delay Line
x4 / x8 PLL
C155P/N
8.5/11.2MHz
C34/C44 RSEL
PCCi
Figure 5 - Output Interface Circuit Block Diagram The T1 and E1 signals are generated from a common DPLL signal. Consequently, all frame pulses and clock outputs are locked to one another for all operating states, and are also locked to the selected input reference in Normal Mode. See Figure 18. All frame pulses and clock outputs have limited driving capability, and should be buffered when driving capacitive loads exceeding 30pF. Input Impairment Monitor This circuit monitors the input signal to the DPLL and automatically enables the Auto-Holdover when the frequency of the incoming signal is outside the AutoHoldover capture range. (See Performance Characteristics - Mode Switching). This includes a complete loss of incoming signal, or a large frequency shift in the incoming signal. When the incoming signal returns to normal, the DPLL is returned to Normal Mode with the output signal locked to the input signal. The holdover output signal in the MT90401 is based on the incoming signal 30ms minimum to 60ms prior to entering the
MS1
MS2
Figure 6 - Control State Machine Block Diagram Master Clock The MT90401 uses an external oscillator as the master timing source. For recommended master timing circuits, see the Applications - Master Clock section.
Control and Mode of Operation
The MT90401 has three possible modes operation, Normal, Holdover and Freerun. of
In hardware mode the Mode/Control Select pins MS2 and MS1 select the mode and method of control as shown in Table 3.
RSEL 0 1
Input Reference PRI SEC
Table 2. Input Reference Selection
9
MT90401
MS2 0 0 1 1 MS1 0 1 0 1 Mode NORMAL HOLDOVER FREERUN Reserved
Data Sheet
Telcordia GR-1244-CORE Stratum 3 requirement of 0.37ppm (255 frame slips per 24 hours). Two factors affect the accuracy of Holdover Mode. One is drift on the Master Clock and the other is jitter on the reference signal. The drift on the Master Clock oscillator propagates unattenuated and causes the same drift on the output clocks. This drift can only be reduced by selecting more stable Master Clock oscillator. For example, a 4.6ppm temperature compensated clock oscillator may have a temperature coefficient of 0.03ppm per degree C. The 10 degc change while in Holdover Mode, will result in an additional offset in frequency accuracy equal to 0.3ppm which is much greater than the internal holdover accuracy of the MT90401 (0.02ppm). The other factor affecting accuracy is large jitter on the reference input prior (30ms to 60ms) to the mode switch. For instance, jitter of 7.5UI at 700Hz may reduce the Holdover Mode accuracy from 0.02ppm to 0.10ppm. Freerun Mode Freerun Mode is typically used when a master clock source is required, or immediately following system power-up before network synchronization is achieved. In Freerun Mode, the MT90401 provides timing synchronization signals which are based on master clock frequency (C20i) only, and are synchronized to the reference signals (PRI SEC). and the not and
Table 3. Operating Modes and States The active reference input (PRI or SEC) is selected by the RSEL pin as shown in Table 2. Refer to Table 4 and Figure 12 for details of the state change sequences. Normal Mode Normal Mode is typically used when a slave clock source, synchronized to the network is required. In Normal Mode, the MT90401 provides timing and frame synchronization signals, which are synchronized to one of two reference inputs (PRI or SEC). The input reference signal may have a nominal frequency of 8kHz, 1.544MHz, 2.048MHz or 19.44MHz. The selection of input references is control dependent as shown in state table 4. The reference frequencies are selected by the frequency control pins/bits FS2 and FS1 as shown in Table 1. Holdover Mode Holdover Mode is typically used when network synchronization is temporarily disrupted. In Holdover Mode, the MT90401 provides timing and synchronization signals, which are not locked to an external reference signal, but are based on storage techniques. The storage value is determined while the device is in Normal Mode and locked to an external reference signal When in Normal Mode, and locked to the input reference signal, a numerical value corresponding to the MT90401 output reference frequency is stored alternately in two memory locations every 30ms. When the device is switched into Holdover Mode, the value in memory from between 30ms and 60ms is used to set the output frequency of the device. The frequency accuracy of Holdover Mode is 0.02ppm, which translates to a worst case 14 frame (125us) slips in 24 hours. This is better than the
10
The accuracy of the output clock is equal to the accuracy of the master clock (C20i). So if a 20ppm output clock is required, the master clock must also be 20ppm. See Applications - Master Clock section. Fast Lock Mode Fast Lock Mode is a submode of Normal Mode, it is used to allow the MT90401 to lock to a reference eight times more quickly than normal. Fast Lock Mode necessarily compromises the wander generation characteristics of the MT90401. When the MT90401 is in Fast Lock Mode and SONET Mode at the same time, the PLL frequency slope is limited to less than 1.9ppm per second.
Data Sheet
Transitions from Freerun Mode or Holdover Mode to Normal Mode Telcordia GR-253-CORE requires SONET Internal Clocks to settle within 100s after transitioning from Freerun Mode or Holdover Mode to Normal Mode. During such a transition, the wander filtering requirements for a SONET Internal Clock are relaxed to make a 100s settling time possible. To meet the GR-253-CORE 100s settling time requirement at power-up and during a transition from Freerun Mode to Normal Mode the MT90401 should be placed in its SDH Mode until lock is achieved. When the PLL indicates lock the MT90401 should be placed in SONET Mode. During a transition from Holdover Mode to Normal Mode, GR-253-CORE requires a SONET Internal Clock to limit the frequency slope to less than 2.9ppm per second. To meet the 100s settling time during such a transition it is necessary to keep the MT90401 in SONET Mode and Fast Lock Mode until lock is achieved. When the PLL indicates lock the MT90401 can be taken out of its Fast Lock Mode. A transition from Holdover Mode to Normal Mode can result in a large initial frequency offset, for example 4.6ppm, between the clock's reference and its output. The 2.9ppm per second frequency slope limit required by GR-253-CORE places a lower limit on the time it takes for a SONET Internal Clock to acquire a new frequency. While the clock is acquiring the new frequency a phase error will accumulate which could cause the clock's settling time to be longer than 100s. GR-1244-CORE and GR-253CORE allow a clock to ignore some of the phase error accumulated during the transition from Holdover Mode to Normal Mode. During a transition from Holdover Mode to Normal Mode, if the MT90401 has not achieved lock within 16 seconds, it is recommended that the PLL be put briefly into its Holdover Mode and then returned to Normal Mode by toggling the MS1 pin or the MS1 control bit. Toggling the PLL into and out of Holdover will clear any accumulated phase error and reduce the settling time.
MT90401
MT90401 Measures of Performance
The following are some synchronizer performance indicators and their corresponding definitions. Jitter Generation Jitter generation is the amount of jitter produced by a PLL and is measured at its output. It is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Jitter generation may also be measured when the device is in a non-synchronizing mode, such as free running or holdover, by measuring the output jitter of the device. Jitter generation is usually measured with various band-limiting filters depending on the applicable standards. Jitter Tolerance Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied jitter magnitude and jitter frequency depends on the applicable standards (see Figures 7, 8 and 9).
Figure 7 - Jitter Tolerance GR-1244 1.544MHz Reference
Figure 8 - Jitter Tolerance ITU-T G.813 Option 1
11
MT90401
Data Sheet
Figure 9 - Jitter Tolerance SONET Category II (OC1) 19.44 MHz Input Reference Jitter Transfer Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. For the MT90401, two internal elements determine the jitter attenuation. This includes the low pass loop filter and the phase slope limiter. Both of these parameters have different settings depending on whether the device is in SONET or SDH mode. For SONET mode the loop filter has a corner frequency of 70 millihertz and the output phase slope is limited to 885ns per second. For SDH mode the loop filter has a corner frequency of 1.1 Hertz and a maximum phase slope of 53ns per 1.326 milliseconds. If the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the maximum output phase slope will be limited. The MT90401 has ten outputs that can be locked to four possible input frequencies for a total of 40 possible jitter transfer functions. Since all outputs are derived from the same internal signal, the jitter transfer values for the four cases, 8kHz to 8kHz, 1.544MHz to 1.544MHz, 2.048MHz to 2.048MHz 19.44 MHz to 19.44 MHz can be applied to all outputs.
Figure 11 - Jitter and Wander Transfer with SDH Filter It should be noted that 1UI at 1.544MHz is 648ns, which is not equal to 1UI at 2.048MHz, which is 488ns. Consequently, a transfer value using different input and output frequencies must be calculated in common units (e.g., seconds) as shown in the following example. Example: What is the T1 and E1 output jitter when the T1 input jitter is 20UI (T1 UI Units) and the T1 to T1 jitter attenuation is 18dB? - A ----- 20
OutputT1 = InputT1 x10 OutputT1 = 20 x10 - 18 ------- 20
= 2.5UI ( T1 )
( 1UIT1 ) OutputE1 = OutputT1 x --------------------( 1UIE1 ) ( 644ns ) OutputE1 = OutputT1 x ------------------- = 3.3UI ( T1 ) ( 488ns ) Using the above method, the jitter attenuation can be calculated for all combinations of inputs and outputs based on the four jitter transfer functions provided. Since intrinsic jitter generation is always present, jitter attenuation will appear to be lower for small input jitter signals than for large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter signals (e.g., 75% of the specified maximum jitter tolerance).
Figure 10 - Jitter and Wander Transfer with SONET filter
12
Data Sheet
MT90401
State Freerun PCCi 0 1 X X X X S0 S1 S1 S2 / / Normal (PRI) S1 S2 MTIE S1H S2H S0 Normal (SEC) S2 S1 MTIE S1 MTIE / S2H S0 / S0 Holdover (PRI) S1H S1 S1 MTIE S2 MTIE Holdover (SEC) S2H S1 MTIE S1 MTIE S2 MTIE / S0
Description Input Controls MS2 0 0 0 0 0 1 MS1 0 0 0 1 1 0 RSEL 0 0 1 0 1 X
Legend: No Change / Not Valid MTIE State change occurs with TIE Corrector Circuit Refer to Control State Diagram for state changes to and from Auto-Holdover State
Table 4. Control State Table
S0 Freerun (10X)
PCCi-0 PCCi-1
S1 Normal Primary (000)
{A}
S1A Auto-Holdover Primary
S2A Auto-Holdover Secondary
{A}
S2 Normal Secondary (001)
(PCCi=0) (PCCi=1) NOTES: (XXX) {A} MS2 MS1 RSEL Invalid Reference Signal
S1H Holdover Primary (010)
S2H Holdover Secondary (011)
Phase Re-Alignment Phase Continuity Maintained (without TIE Corrector Circuit) Phase Continuity Maintained (with TIE Corrector Circuit)
Movement to Normal State from any state requires a valid input signal
Figure 12 - Control State Diagram
13
MT90401
Frequency Accuracy Frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. For the MT90401, the Freerun accuracy is equal to the Master Clock (C20i) accuracy. Holdover Accuracy Holdover accuracy is defined as the absolute tolerance of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techniques. For the MT90401, the storage value is determined while the device is in Normal Mode and locked to an external reference signal. The initial frequency offset of the MT90401 in Holdover Mode is +20 x 10-9. This is more accurate than Telcordia's GR-1244-CORE stratum 3 requirements of +50 x 10-9. Once the MT90401 has transitioned into Holdover Mode, holdover stability is determined by the stability of the 20MHz Master Clock Oscillator. The absolute Master Clock (C20i) accuracy of the MT90401 does not affect Holdover accuracy, but the change in C20i accuracy while in Holdover Mode does. Capture Range Lock Range
Data Sheet
This is the input frequency range over which the synchronizer must be able to maintain synchronization. The lock range is equal to the capture range for the MT90401. Phase Slope Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect to an ideal signal. The given signal is typically the output signal. An ideal signal is one that is at exactly the nominal frequency and is completely free of jitter and wander. Frequency Slope Frequency slope is measured in ppm per second and is the rate at which the fractional frequency offset of a given signal changes. The fractional frequency offset is calculated with respect to an ideal signal. The given signal is typically the output signal. An ideal signal is one that is at exactly the nominal frequency and is completely free of jitter and wander. Time Interval Error (TIE) TIE is the time delay between a given timing signal and an ideal timing signal. Maximum Time Interval Error (MTIE)
Also referred to as pull-in range. This is the input frequency range over which the synchronizer must be able to pull into synchronization. The MT90401 capture range is equal to 52 ppm minus the accuracy of the master clock (C20i). For example, a 32 ppm master clock results in a capture range of 20 ppm. In Telcordia GR-1244-CORE, it is a conditional requirement that the PLL should be able to reject references that are off the nominal frequency by more than 17ppm. MT90401 provides two pins and two bits, PRIOOR and SECOOR, to indicate whether the primary and secondary reference are within the 17ppm of the nominal frequency. When the accuracy of the 20MHz oscillator is 4.6ppm the effective out of range limits of the PRIOOR and SECOOR pins will be +16.6ppm to -7.4ppm or +7.4ppm to -16.6ppm. Both references are monitored at the same time. PRIOOR and SECOOR are updated every 1.0 to 1.5 seconds.
MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a particular observation period. MTIE ( S ) = TIEmax ( t ) - TIEmin ( t ) Phase Continuity Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency. Phase continuity applies to the output of the synchronizer after a signal disturbance due to a reference switch or a mode change. Phase Lock Time This is the time it takes the synchronizer to phase lock to the input signal. Phase lock occurs when the input signal and output signal are not changing in phase with respect to each other (not including jitter).
14
Data Sheet
Lock time is very difficult to determine because it is affected by many factors which include: i) initial input to output phase difference ii) initial input to output frequency difference iii) synchronizer loop filter iv) synchronizer limiter Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements. For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock time. And better (smaller) phase slope performance (limiter) results in longer lock times. The MT90401 loop filter and limiter were optimized to meet the GR-253-CORE, GR-1244CORE, and G-813 jitter transfer and phase slope requirements.
MT90401
timing source is 20 ppm, then the capture range will be 32 ppm.
TIE Correction (using PCCi) When Primary Holdover Mode is entered for short time periods, TIE correction should not be enabled. This will prevent unwanted accumulated phase change between the input and output. For example, we can estimate phase accumulation for a case when ten Normal to Holdover to Normal sequential mode changes occur, with each Holdover entered for 2s with TIE enabled. Each mode change could account for a phase shift as large as 250ns. Thus, the accumulated phase could be as large as 2.9us, and, the overall MTIE could be as large as 2.9us. Phase hold = 0.02ppm x 2s = 40ns Phase state = 50ns + 200ns = 250ns Phase
* * *
MT90401 and Network Specifications
The MT90401 meets all applicable PLL requirements for the following specifications. 1. Telcordia GR-1244-CORE December 2000 for Stratum 3, SONET Minimum Clock (SMC), Stratum 4 Enhanced and Stratum 4 2. Telcordia GR-253-CORE September 2000 for SONET Internal Clocks 3. ANSI T1.101 (DS1) February 1994 for Stratum 3, Stratum 4 Enhanced and Stratum 4 4. ANSI T1.105.09-1996 for SONET Minimum Clocks (SMCs) 5. ITU-T G.813 August 1996 for Option1 and Option 2 clocks (with external jitter attenuator)
10
= 10 x ( 250ns + 40ns ) = 2.9us
0.02ppm is the accuracy of Holdover Mode 50ns is the maximum phase continuity of the MT90401 from Normal Mode to Holdover Mode 200ns is the maximum phase continuity of the MT90401 from Holdover Mode to Normal Mode (with or without TIE Corrector Circuit)
Applications
This section contains MT90401 application specific details for Master clock operation, LVDS output drivers setup, microport functionality and output clock phase adjustment. Master Clock In Freerun Mode, the frequency tolerance at the clock outputs is identical to the frequency tolerance of the source at the C20i input pin. Another consideration in determining the accuracy of the master timing source is the desired capture range. The sum of the accuracy of the master timing source and the capture range of the MT90401 will always equal 52ppm. For example, if the master
When the same ten Normal to Holdover to Normal mode changes occur with TIE disabled, the overall MTIE will only be 250ns. There would be no accumulated phase change, since the input to output phase is re-aligned after every Holdover to Normal state change.
15
MT90401
C155 clock generation and LVDS output drivers The MT90401 provides a 155.52MHz clock that is frequency locked to the internally generated 19.44MHz clock. The locking of both clocks is achieved by the internal analog PLL that multiplies the 19.44MHz clock eight times. This C155 clock is output on pins C155P and C155N in LVDS format. The LVDS offset voltage Vos is set by applying an external 1.25V reference voltage to the Vref input (pin 33). This pin can be connected to a common 1.25V voltage reference that may exist on the customer board or alternatively can be generated by a simple voltage divider as it is shown in Figure 13 LVDS Voltage Offset Vos Generation Circuit. To ensure proper operation of LVDS drivers, the decoupling capacitor must be placed very close to the MT90401 package. Microport
Data Sheet
If the HW pin is tied low, an 8 bit Motorola microprocessor may be used to control the PLL and report on the device status. In this case the control pins SONET/SDH, RSEL, MS1, MS2, FS1, FS2, and FLOCK are unused and they are replaced by the control bits SONET/SDH, RSEL, MS1, MS2, FS1, FS2, FLOCK. The input pin PCCi remains in use. The output pins LOCK, HOLDOVER, SECOOR, PRIOOR function whether the device is in microprocessor mode or hardware mode, but these signals are also available in Status Register 1. The microport provides additional functionality not available in hardware. Output Phase Adjustment Two control registers are available to program the output phase offset of the generated clocks. All 16.384 MHz derived outputs clocks, F16o, F80, F0o, C16o, C8o, C4o and C2o can be collectively shifted up to 125 microseconds with a step size of 60 nS with respect to the input reference by programming the Set Delay Word 1 and Set Delay Word 2 registers.
Figure 13 - LVDS Voltage Offset Vos Generation Circuit
16
Data Sheet
Control and Status Registers
Address (A6A5A4A3A2A1A0) 00H (Table 6) 01H (Table 7) 02H 03H 04H (Table 8) 05H 06H (Table 9) 07H (Table 10) 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH (Table 11) 10H Register Control Register 1 Status Register 1 Reserved Reserved Control Register 2 Reserved Set Delay Word 2 Set Delay Word 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Identification Word Reserved Read/ Write Function
MT90401
Read/ RSEL, FS2, FS1, MS2, MS1, SONET/SDH Write FLOCK, TCLR Read PRIOOR, SECOOR, LOCK, Only RSV, FLim, RSV, RSV Read Only Read Only Read/ E3/DS3/OC3, E3/DS3, RSV=0, Write RSV=0, RSV=0, RSV=0, RSV=0. Read / Set all bits to zero. Write Read/ RSV=0, RSV=0, RSV=0, RSV=0, Write C16OCNT10,C16OCNT9, C16OCNT8 Read/ C16OCNT7-0 Write Read/ Set all bits to zero. Write Read Only Read Only Read Only Read Only Read Only Read Only Read ID7-0 Only Read/ Set all bits to zero. Write Table 5. Register Map OffEn, RSV=0, HOLDOVER,
17
MT90401
Bit 7 6-5 Name RSEL FS2-1 Functional Description
Data Sheet
Reference Select. A zero selects the PRI (primary) reference source as the input reference signal and a one selects the SEC (secondary) reference. Frequency Select 2 - 1. These bits select which of four possible frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be input to the PRI and SEC inputs. FS2 - 0, FS1 - 0 = 19.44 MHz FS2 - 0, FS1 - 1 = 8 kHz. FS2 - 1, FS1 - 0 = 1.544 MHz. FS2 - 1, FS1 - 1 = 2.048 MHz. Mode Select 2 - 1: These bits select the PLL state of operation. MS2 - 0, MS1 - 0 = Normal. MS2 - 0, MS1 - 1 = Holdover. MS2 - 1, MS1 - 0 = Freerun. MS2 - 1, MS1 - 1 = Reserved. SONET / SDH. Set to one to move the loop filter corner frequency to 70 millihertz and limit the phase slope to 885 ns per second as per SONET requirements. Set to zero to move the corner frequency to 1.1 Hz and limit the phase slope to 53ns per 1.326ms. Fast Lock. Set to one to allow the PLL to lock faster than normal to the input reference. During the time that FLOCK is one, the wander generation of the PLL is, of necessity, compromised. Set to zero for normal operation. TIE Clear. Set to zero to clear the Time Interval Error correction circuit resulting in a realignment of output phase with input phase. When this bit is zero, the Time Interval Error correction circuit is disabled. When this bit is one, the Time Interval Error correction circuit will function normally. Table 6. Control Register 1 (Address 00H - Read/Write)
4-3
MS2-1
2
SONET/SDH
1
FLOCK
0
TCLR
Bit 7
Name PRIOOR
Functional Description Primary Out Of Range. A one indicates that the primary reference is off the PLL center frequency by more than 12 ppm. The measurement is done on a 1 second basis using a signal derived from the 20MHz clock input on C20i. When the accuracy of the 20MHz clock is 4.6ppm, the effective out of range limits of the PRIOOR signal will be +16.6ppm to -7.4ppm or +7.4ppm to -16.6ppm. Secondary Out of Range. A one indicates that the secondary reference is off the PLL center frequency by more than 12 ppm. The measurement is done on a 1 second basis using a signal derived from the 20MHz clock input on C20i. When the accuracy of the 20MHz clock is 4.6ppm, the effective out of range limits of the PRIOOR signal will be +16.6ppm to -7.4ppm or +7.4ppm to -16.6ppm. Lock. This bit goes high when the PLL is in frequency lock to the input reference. Holdover. This bit goes high whenever the device is in Holdover mode. Reserved. Frequency Limit. This bit goes high whenever the reference frequency hits the input frequency offset tolerance of the PLL. This bit can flicker high in the event of large excursions of still tolerable input jitter. Reserved. Table 7. Status Register 1 (Address 01H - Read Only)
6
SECOOR
5 4 3 2
LOCK HOLDOVER RSV FLim
1-0
RSV
18
Data Sheet
Bit 7 Name E3DS3/OC3 Functional Description
MT90401
E3DS3/OC3 Selection. Set this bit to zero to enable the differential 155.52 MHz output clock on the C155N/C155P pins and cause the C34/C44 pin to output its nominal clock frequency divided by 4. Set this bit to one to disable the differential 155.52 MHz output clock on the C155N/C155P pins and cause the C34/C44 pin to output its nominal clock frequency. E3/DS3. Set this bit low to select a clock rate of 44.736 MHz for the C34/C44 pin. Set high to select a clock rate of 34.368 MHz for the C34/C44 pins. Reserved. Set to zero for normal operation.
6 5-0
E3/DS3 RSV
Table 8. Control Register 2 (Address 04H - Read/Write) Bit 7-4 3 2-0 Name RSV OffEn Reserved. Set to zero. Offset Enable. Set high to enable a programmed phase shift between the input reference and the generated clocks. Functional Description
C16OCNT10-8 C16 Offset Count. The three most significant bits of the offset delay word. These bits program the offset all clocks derived from 16.384 MHz with respect to the input reference in step sizes of 60 nS. Table 9. Set Delay Word 2 (Address 06H - Read/Write)
Bit 7-0
Name C16OCNT 7-0
Functional Description C16 Offset Count. The eight least significant bits of the offset delay word. These bits program the offset of all clocks derived from 16.384 MHz with respect to the input reference in step sizes of 60 nS.
Table 10. Set Delay Word 1 (Address 07H - Read/Write)
Bit 7- 0
Name ID7-0
Functional Description Identification Word 7-0. These bits contain the revision number of the part. Table 11. Identification Word (Address 0FH - Read Only)
19
MT90401
Absolute Maximum Ratings*
Parameter 1 2 3 4 5 Supply voltage Voltage on any pin Current on any pin Storage temperature 80 LQFP package power dissipation Symbol VDDR VPIN IPIN TST PPD -55 Min -0.3 -0.3
Data Sheet
Max 7.0 VDD+0.3 30 125 1000
Units V V mA C mW
* Voltages are with respect to ground (V SS ) unless otherwise stated. * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions*
Characteristics 1 Supply voltage 2 Operating temperature Sym VDD TA Min 3.0 -40 Typ 3.3 25 Max 3.6 +85 Units V 0C
* Voltages are with respect to ground (V SS) unless otherwise stated.
DC Electrical Characteristics*
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 Supply current with C20i = 0V Supply current with C20i = 20MHz CMOS high-level input voltage CMOS low-level input voltage Input leakage current High-level output voltage Low-level output voltage LVDS Differential Output Voltage LVDS Change in VOD between complementary output states LVDS Offset Voltage LVDS Change in VOS between complementary output states LVDS Output short circuit current LVDS Output Rise/Fall Times Sym IDDS IDD VCIH VCIL IIL VOH VOL VOD dVOD VOS dVOS IOS TRF 300 1.15 250 2.4 0.4 460 40 1.35 40 20 600 0.7VDD 0.3VDD 15 Min Max 2 150 Units mA mA V V A V V mV mV V mV mA ps VCI55P = 0 or VC155N = 0 Measured at 20% and 80% VI=VDD or 0V IOH= 10 mA IOL= 10 mA ZT = 100 Conditions/Notes Outputs unloaded Outputs unloaded
* Voltages are with respect to ground (V SS ) unless otherwise stated. * Supply voltage and operating temperature are as per Recommended Operating Conditions.
20
Data Sheet
MT90401
AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels*
Characteristics 1 2 3 Threshold Voltage Rise and Fall Threshold Voltage High Rise and Fall Threshold Voltage Low Sym VT VHM VLM CMOS 0.5VDD 0.7VDD 0.3VDD Units V V V
* Voltages are with respect to ground (V SS) unless otherwise stated. * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Timing for input and output signals is based on the worst case
Timing Reference Points ALL SIGNALS tIF, tOF tIR, tOR VHM VT V LM
Figure 14 - Timing Parameter Measurement Voltage Levels
AC Electrical Characteristics - Microprocessor Timing*
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 DS low DS High CS Setup R/W Setup Address Setup CS Hold R/W Hold Address Hold Data Delay Read Data Hold Read Data Setup Write Data Hold Write Sym tDSL tDSH tCSS tRWS tADS tCSH tRWH tADH tDDR tDHR tDSW tDHW 0 10 Min 30 30 0 18 0 0 4 10 50 30 Max Units ns ns ns ns ns ns ns ns ns ns ns ns CL=150pF Test Conditions
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
21
MT90401
Data Sheet
tDSL DS tDSH tCSS CS tRWS R/W tADS A0-A4 tDDR D0-D7 READ tDSW D0-D7 WRITE VALID DATA tDHW VALID DATA tDHR VTT VTT,VCT tADH VTT tRWH tCSH VTT VTT
VTT
Note: DS and CS may be connected together.
Figure 15 - Microport Timing
tR8D PRI/SEC 8kHz PRI/SEC 1.544MHz PRI/SEC 2.048MHz tR15D tRW tRW VT
tR2D
tRW
VT
F8o NOTES: 1. Input to output delay values are valid after a TCLR or RST with no further state changes
VT
Figure 16 - Input to Output Timing for T1/E1 signals (Normal Mode)
tR19D tR19W PRI/SEC 19.44MHz C19o VT tR19W VT
Figure 17 - Input to Output Timing for 19.44MHz Signal (Normal Mode)
22
Data Sheet
AC Electrical Characteristics - Output Timing*
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Reference input pulse width high or low (8KHz, 1.544MHz, 2.048MHz) Reference input pulse width high or low (19.4MHz) Reference input rise or fall time 8kHz reference input to F8o delay 1.544MHz reference input to F8o delay 2.048MHz reference input to F8o delay 19.44MHz reference input to C19o delay F8o to F0o delay F8o to F16o delay F8o to C1.5o delay F8o to C6o delay F8o to C2o delay F8o to C4o delay F8o to C8o delay F8o to C16o delay C1.5o pulse width high or low C6o pulse width high or low C2o pulse width high or low C4o pulse width high or low C8o pulse width high or low C16o pulse width high or low C19o pulse width high or low C19o to c155 delay F0o pulse width low F8o pulse width high F16o pulse width low Output clock and frame pulse rise or fall time Input Controls Setup Time Input Controls Hold Time C34o Pulse width low or high C44o Pulse width low or high C8.5o Pulse width low C11o Pulse width low Sym tRW tR19W tIR,tIF tR8D tR15D tR2D tR19D tF0D tF16D tC15D tC6D tC2D tC4D tC8D tC16D tC15W tC6W tC2W tC4W tC8W tC16W tC19W tC155D tF0WL tF8WH tF16WL tOR,tOF tS tH tC34W tC44W tC8.5WL tC11WL 100 100 9 6 106 81 -85 400 220 38 115 23 -100 58 -6 -6 -6 -6 315 70 235 115 53 24 9 0 235 115 55 6 250 130 63 9 Min 100 10 10 -65 425 230 42 125 35 -85 70 5 5 5 5 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MT90401
Conditions/Notes
* Supply voltage and operating temperature are as per Recommended Operating Conditions
23
MT90401
tF8WH F8o tF0WL F0o tF16WL F16o tC16WL C16o tC8W C8o tC4W C4o tC2W C2o tC6W C6o tC6W tC6D tC2D tC4W tC4D tC8W tC8D tF16D tF0D
Data Sheet
VT
VT
VT
tC16D
VT
VT
VT
VT
VT
tC15W C1.5o
tC15D VT
Figure 18 - Output Timing 1
tC19W C19o tC155D C155p C155n tC155D
tC19W VT VLVH VLVL
Figure 19 - Output Timing 2
F8o tS MS1,2, RSEL, PCCi tH
VT
VT
Figure 20 - Input Controls setup and Hold Timing
24
Data Sheet
tC34W C34o
MT90401
VT
tC44W C44o VT
tC 8.5 VT C8.5o
tC11 VT C11o
Figure 21 - Output Timing 3
AC Electrical Characteristics - C20i Master Clock Input*
Characteristics 1 2 3 Duty cycle Rise time Fall time Sym Min 40 Max 60 10 10 Units % ns ns Conditions/Notes
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
25
MT90401
Performance Characteristics: Mode Switching*
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Phase lock time Output phase continuity with: reference switch mode switch to Normal mode switch to Freerun mode switch to Holdover Output phase slope - SDH mode - SONET mode Reference input for Auto-Holdover with: 8kHz -30k -30k -30k -30k Capture range with C20i at: Holdover Mode accuracy with C20i at: 0ppm 20ppm 0ppm 20ppm Min -0.02 -0.02 -52 -32 100 200 200 200 50 40 885 +30k +30k +30k +30k Typ Max +0.02 +0.02 +52 +32 Units ppm ppm ppm ppm s ns ns ns ns us/s ns/s ppm ppm ppm ppm
Data Sheet
Conditions/Notes
4.6ppm frequency offset
53ns per 1.326ms
1.544MHz 2.048MHz 19.44MHz
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
Performance Characteristics: Output Jitter Generation - Filtered
Characteristics 1 2 3 4 5 6 7 8 Intrinsic jitter at C1.5o (1.544MHz) Intrinsic jitter at C2o (2.048MHz) Intrinsic jitter at C19o (19.44MHz) Intrinsic jitter at C19o (19.44MHz) Intrinsic jitter at C34o (34.368MHz) Intrinsic jitter at C34o (34.368MHz) Intrinsic jitter at C44o (44.736MHz) Intrinsic jitter at C44o (44.736MHz) MAX UIpp 0.004 0.004 0.100 0.100 0.044 0.039 0.044 0.037 MAX ns-pp 2.76 1.83 5.20 5.16 1.30 1.15 0.99 0.82 Notes Filter: 10Hz - 40kHz Filter: 20Hz - 100kHz Filter: 500Hz - 1.3MHz OC-3 Filter: 65kHz - 1.3MHz OC-3 Filter: 100Hz - 800kHz Filter: 10kHz - 800kHz Filter: 10Hz - 400kHz Filter: 30kHz - 400kHz
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
26
Data Sheet
Performance Characteristics: Output Jitter Generation - Filtered
(VDD = 3.3V +/- 10%, TA = -5C to +85C) Characteristics 1 2 3 4
.
MT90401
MAX UIpp 0.12 0.11 0.18 0.13
MAX ns-pp 0.76 0.69 1.13 0.83
Notes Filter: 100Hz - 400kHz OC-1 Filter: 20kHz - 400kHz OC-1 Filter: 500Hz - 1.3MHz OC-3 Filter: 65kHz - 1.3MHz OC-3
Intrinsic jitter at C155o (155.52MHz) Intrinsic jitter at C155o (155.52MHz) Intrinsic jitter at C155o (155.52MHz) Intrinsic jitter at C155o (155.52MHz)
Performance Characteristics: Output Jitter Generation - Unfiltered*
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Intrinsic jitter at C1.5o (1.544MHz) Intrinsic jitter at C2o (2.048MHz) Intrinsic jitter at C4o (4.096MHz) Intrinsic jitter at C6o (6.312MHz) Intrinsic jitter at C8o (8.192MHz) Intrinsic jitter at C8.5o (8.592MHz) Intrinsic jitter at C11o (11.184MHz) Intrinsic jitter at C16o (16.384MHz) Intrinsic jitter at C19o (19.44MHz) Intrinsic jitter at C34o (34.368MHz) Intrinsic jitter at C44o (44.736MHz) Intrinsic jitter at C155o (155.52MHz) Intrinsic jitter at F0o (8kHz) Intrinsic jitter at F8o (8kHz) Intrinsic jitter at F16o (8kHz) Sym MAX : UIpp 0.010 0.012 0.027 0.037 0.048 0.032 0.036 0.096 0.11 0.12 0.12 0.21 NA NA NA MAX : nspp 6.5 5.8 6.5 5.8 5.9 3.8 3.2 5.8 5.6 3.5 2.6 1.3 4.7 4.0 3.1 Notes
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
27
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